1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device comprising a silicon and silicon-germanium stacked film structure suitable to miniaturization of a gate electrode and a method for manufacturing the same.
2. Description of the Related Art
Attention has now been paid to the technique of using a silicon and silicon-germanium stacked film (hereinafter referred to as an Si/SiGe) as a gate electrode of MOSFET (metal oxide semiconductor field effect transistor (hereinafter referred to as MOS)). A properly formed Si/SiGe gate electrode has various advantages, for example, suppressing a formation of a depletion layer in the gate electrode and improving current driving capability of p-type MOSFET (hereinafter referred to as pMOS).
However, there is a problem that resistance of a silicide being formed on the gate electrode is increased if the Ge concentration in the upper surface of the gate electrode is increased. Thus the surface Ge concentration of the gate electrode prior to the formation of the silicide is preferably low. In order to solve this problem, a technique for forming a poly-Si layer on the SiGe layer is disclosed in JPN PAT APPLN KOKAI PUBLICATION NO. 2002-26318. The patent further discloses another technique for controlling a cross-sectional configuration of the gate electrode by thermally oxidizing the gate electrode to provide a T-shaped gate configuration. However, no reference is made to the application of this technique to the complementary MOSFET (hereinafter referred to as a CMOS).
In order to apply the SiGe gate electrode to CMOS, there are further problems to be solved. To improve the current driving capability of pMOS, it is preferable to increase the Ge concentration in the gate electrode, in particular, near an interface to the gate insulator. In nMOS, however, if the Ge concentration near the interface to the gate insulator is increased, the current driving capability is lowered, thus presenting a problem just opposite to that in pMOS. Therefore, there remains a task to be solved, that is, a task such that the Ge concentration in the gate electrode is properly controlled in pMOS and nMOS, respectively.
A technique to control Ge concentration profiles in the Si/SiGe gate electrode of pMOS and nMOS in CMOS is disclosed by Hwa Sung Rhee et. al. in a paper entitled “A New Double-Layered Structure for Mass-Production-Worthy CMOSFETs with Ploy-SiGe Gate”, 2002 Symposium on VLSI Technology Digest of Technical Papers, 13.3, pp. 126–127. That is, by controlling a polycrystalline structure in a p-type gate electrode, the polycrystalline structure is formed to be different from that in an n-type gate electrode. As a result, the Ge concentration in the SiGe film in the p-type gate electrode is maintained at a higher level. That is, when the Si/SiGe gate electrode is crystallized, the crystal grain size in the lower SiGe layer is made smaller in pMOS while the crystal grain size of the upper Si layer is made larger in pMOS. In nMOS, the crystal grain size is not controlled, so that the lower SiGe layer and upper Si layer both have a smaller crystal grain size. In this way, density of a crystal grain boundary, which acts as a diffusion path of Ge in the gate electrode, is controlled to less in pMOS gate electrode and more in nMOS gate electrode. As a result, the Ge concentration near a gate electrode/gate insulator interface can be made higher only in pMOS gate electrode. To provide the above-mentioned crystal grain size distribution, pMOS gate electrode is formed not as a conventional continuous deposition of polycrystalline SiGe film and polycrystalline Si film but as a four-layered deposition including a lower polycrystalline SiGe film, an intermediate amorphous Si film, an intermediate amorphous SiGe film and an upper amorphous Si film. Then the four-layered structure is crystallized to form a controlled crystal grain size described above. For this reason, the manufacturing process becomes complex, thus presenting a problem.
With the miniaturization of the CMOS semiconductor device, a problem occurs in the formation of an extension of a source/drain near edge of the gate electrode to lessen a short channel effect. In the conventional method for providing an extension by implantation after the formation of the gate electrode, horizontal diffusion length of the extension below the gate electrode is greater in pMOS than in nMOS, so that their overlap amounts are different. This is caused by the difference in diffusion coefficient between p-type and n-type dopants introduced into the extensions. To solve the problem, for example, proposals are made by which, a thicker offset spacer is formed in pMOS than in nMOS after the formation of the gate electrode, a heat treatment of pMOS is made at a lower temperature than that of nMOS, or the like. Even in either case, the complex process or lowering of a device performance is unavoidable.
Therefore, there is a need for a gate electrode and its formation technique suitable to the miniaturized CMOS semiconductor device. For pMOS and nMOS, there is a growing demand for a technique for properly controlling a Ge concentration in the respective Si/SiGe electrode as well as the technique for properly controlling an overlap amount between the extension and the gate electrode.